The expression “phase tracker” is used herein to denote a sampling position selection circuit that monitors the relative phase of a data signal and an oversampling clock (employed to oversample the data signal), selects a best sampling position (for oversampling the data signal) as a result of this monitoring, and updates the selected sampling position from time to time (e.g., periodically).
As used herein, the expression “sampling position” contemplates that a data signal is oversampled using an oversampling clock having N sampling edges for each data period of the data signal, where there is a phase difference of 360/N degrees between the “i”th sampling edge and the “(i+1)”th sampling edge of the oversampling clock (where “i” is an integer, and N is an integer greater than one), and the data period is equal to 1/(the data signal's bit rate). Each of the N edges for each data period belongs to a different “sampling position.” Thus, the oversampling clock has N sets of sampling edges, each set having a different phase (relative to any arbitrarily selected edge of the oversampling clock). Each such set of sampling edges is denoted herein as a “sampling position.”
The term “receiver” is used herein in a broad sense to denote any device capable of receiving and decoding data that has been transmitted over a link (e.g., a serial link) and optionally also performing additional functions, which can include decrypting the received data and other operations related to decoding, reception, or decryption of the received data. For example, the term receiver can denote a transceiver that performs the functions of a transmitter as well as the functions of a receiver.
The terms “data” and “data signal” are used in a broad sense herein (in the context of sampling of “data” or a “data signal”) to denote any signal capable of being oversampled. Examples of a data signal are a signal indicative of a clock, and a signal indicative of an arbitrary sequence of binary bits of information (also referred to as binary bits of data).
The expression “center of the data eye” (of a data signal indicative of binary data) is used herein to denote the optimal phase at which to sample the data signal. When the data signal is indicative of a periodic sequence of “zero” bits alternating with “one” bits, the center of the data eye is 180 degrees out of phase with the transitions between the zero bits and one bits. More generally, when the data signal has constant bit rate and is indicative of any sequence of “zero” and “one” bits (including many transitions between zero bits and one bits), the center of the data eye is 180 degrees out of phase with the transitions between the zero bits and one bits (i.e., 180 degrees out of phase with a periodic signal that is aligned with the transitions between the zero bits and one bits).
Various serial links for transmitting data and clock signals are well known.
One conventional serial link, used primarily for high-speed transmission of video data from a host processor (e.g., a personal computer) to a monitor, is known as a transition minimized differential signaling interface (“TMDS” link). The characteristics of a TMDS link include the following:
1. video data are encoded and then transmitted as encoded words (each 8-bit word of digital video data is converted to an encoded 10-bit word before transmission);                a. the encoding determines a set of “in-band” words and a set of “out-of-band” words (the encoder can generate only “in-band” words in response to video data, although it can generate “out-of-band” words in response to control or sync signals. Each in-band word is an encoded word resulting from encoding of one input video data word. All words transmitted over the link that are not in-band words are “out-of-band” words);        b. the encoding of video data is performed such that the in-band words are transition minimized (a sequence of in-band words has a reduced or minimized number of transitions);        c. the encoding of video data is performed such that the in-band words are DC balanced (the encoding prevents each transmitted voltage waveform that is employed to transmit a sequence of in-band words from deviating by more than a predetermined threshold value from a reference potential. Specifically, the tenth bit of each “in-band” word indicates whether eight of the other nine bits thereof have been inverted during the encoding process to correct for an imbalance between running counts of ones and zeroes in the stream of previously encoded data bits);        
2. the encoded video data and a video clock signal are transmitted as differential signals (the video clock and encoded video data are transmitted as differential signals over conductor pairs);
3. three conductor pairs are employed to transmit the encoded video, and a fourth conductor pair is employed to transmit the video clock signal; and
4. signal transmission occurs in one direction, from a transmitter (typically associated with a desktop or portable computer, or other host) to a receiver (typically an element of a monitor or other display device).
A use of the TMDS serial link is the “Digital Visual Interface” interface (“DVI” link) adopted by the Digital Display Working Group. It will be described with reference to FIG. 1. A DVI link can be implemented to include two TMDS links (which share a common conductor pair for transmitting a video clock signal) or one TMDS link, as well as additional control lines between the transmitter and receiver. The DVI link of FIG. 1 includes transmitter 1, receiver 3, and the following conductors between the transmitter and receiver: four conductor pairs (Channel 0, Channel 1, and Channel 2 for video data, and Channel C for a video clock signal), Display Data Channel (“DDC”) lines for bidirectional communication between the transmitter and a monitor associated with the receiver in accordance with the conventional Display Data Channel standard (the Video Electronics Standard Association's “Display Data Channel Standard,” Version 2, Rev. 0, dated Apr. 9, 1996), a Hot Plug Detect (HPD) line (on which the monitor transmits a signal that enables a processor associated with the transmitter to identify the monitor's presence), Analog lines (for transmitting analog video to the receiver), and Power lines (for providing DC power to the receiver and a monitor associated with the receiver). The Display Data Channel standard specifies a protocol for bidirectional communication between a transmitter and a monitor associated with a receiver, including transmission by the monitor of an Extended Display Identification (“EDID”) message that specifies various characteristics of the monitor, and transmission by the transmitter of control signals for the monitor. Transmitter 1 includes three identical encoder/serializer units (units 2, 4, and 6) and additional circuitry (not shown). Receiver 3 includes three identical recovery/decoder units (units 8, 10, and 12) and inter-channel alignment circuitry 14 connected as shown, and additional circuitry (not shown).
As shown in FIG. 1, circuit 2 encodes the data to be transmitted over Channel 0, and serializes the encoded bits. Similarly, circuit 4 encodes the data to be transmitted over Channel 1 (and serializes the encoded bits), and circuit 6 encodes the data to be transmitted over Channel 2 (and serializes the encoded bits). Each of circuits 2, 4, and 6 responds to a control signal (an active high binary control signal referred to as a “data enable” or “DE” signal) by selectively encoding either digital video words (in response to DE having a high value) or a control or synchronization signal pair (in response to DE having a low value). Each of encoders 2, 4, and 6 receives a different pair of control or synchronization signals: encoder 2 receives horizontal and vertical synchronization signals (HSYNC and VSYNC); encoder 4 receives control bits CTL0 and CTL1; and encoder 6 receives control bits CTL2 and CTL3. Thus, each of encoders 2, 4, and 6 generates in-band words indicative of video data (in response to DE having a high value), encoder 2 generates out-of-band words indicative of the values of HSYNC and VSYNC (in response to DE having a low value), encoder 4 generates out-of-band words indicative of the values of CTL0 and CTL1 (in response to DE having a low value), and encoder 6 generates out-of-band words indicative of the values of CTL2 and CTL3 (in response to DE having a low value). In response to DE having a low value, each of encoders 4 and 6 generates one of four specific out-of-band words indicative of the values 00, 01, 10, or 11, respectively, of control bits CTL0 and CTL1 (or CTL2 and CTL3).
Each of the out-of-band control words (indicative of CTL0 and CTL1, or CTL2 and CTL3) is encoded as a 10-bit, transition-maximized code word indicative of two control bits (CTL0 and CTL1, or CTL2 and CTL3). Each of the out-of-band sync words (indicative of HSYNC and VSYNC) is encoded as a 10-bit, transition-maximized code word indicative of two sync bits (HSYNC and VSYNC).
In operation of the FIG. 1 system, a cable comprising connectors 20 and 21 and conductors 22 is connected between transmitter 1 and receiver 3. Conductors 22 include a conductor pair for transmitting serialized data over Channel 0 from encoder 2 to decoder 8, a conductor pair for transmitting serialized data over Channel 1 from encoder 4 to decoder 10, a conductor pair for transmitting serialized data over Channel 2 from encoder 6 to decoder 12, and a conductor pair for transmitting a video clock over Channel C from transmitter 1 to receiver 3. Conductors 22 also include wires for the DDC channel (which can be used for bidirectional I2C communication between transmitter 1 and receiver 3), a Hot Plug Detect (HPD) line, “Analog” lines for analog video transmission from transmitter 1 to receiver 3, and “Power” lines for provision of power from transmitter 1 to a receiver 3.
In the FIG. 1 system, the frequency of the video clock signal transmitted over Channel C is typically one-tenth the bit rate at which data transmission occurs over each of the data channels (Channels 0, 1, and 2), in the sense that ten data bits are transmitted over each data channel during each video clock period. This can be accomplished by employing nine delay cells in the transmitter to generate nine multiphase delayed versions of the video clock, and using the nine delayed versions of the video clock (each having a different phase) together with the video clock itself to transmit data over each of Channels 0, 1, and 2, at a rate of ten bits per video clock period.
In receiver 3, the data signal received on Channel 0 is sampled in unit 8, the data signal received on Channel 1 is sampled in unit 10, and the data signal received on Channel 2 is sampled in unit 12. The samples are decoded to recover data, control, or sync bits, and the decoded bits are asserted to circuitry 14.
Another serial link is the “High Definition Multimedia Interface” interface (sometimes referred to as an “HDMI” link or interface) developed Silicon Image, Inc., Matsushita Electric, Royal Philips Electronics, Sony Corporation, Thomson Multimedia, Toshiba Corporation, and Hitachi.
Other serial links include the set of serial links known as Low Voltage Differential Signaling (“LVDS”) links (e.g., “LDI,” the LVDS Display Interface), each of which satisfies the TIA/EIA-644 standard or the IEEE-1596.3 standard, ethernet links, fiberchannel links, serial ATA links used by disk drives, and others.
To recover data transmitted over links (e.g., TMDS links or other serial links), the received data signals are often oversampled. Phase tracking has an important role in data recovery (e.g., recovery of high-speed serial data) performed by blind oversampling systems. Phase tracking determines the relative phase of a received data signal and the oversampling clock employed to oversample the data signal, and picks a best sampling position (i.e., the best relative phase between the data signal and the clock edges at which the data signal is sampled).
U.S. Pat. No. 5,905,769, issued May 18, 1999, describes a conventional phase tracking method and apparatus. The circuitry described with reference to FIG. 6 of U.S. Pat. No. 5,905,769 implements a phase tracking algorithm in connection with 3× oversampling of a data signal having a data period equal to 1/(the data signal's bit rate), and employs a digital PLL circuit to accomplish phase alignment of the oversampling clock with the data signal and to select one “best” sample of each set of three samples obtained per data period.
Phase trackers have an important role in the data recovery process implemented by high-speed serial data receivers. However, there are many issues that make their design difficult, including the following three. First, the input data frequency that the phase tracker has to handle generally ranges over a wide frequency range (e.g., from 25 MHz to 220 MHz in some applications), but the characteristics of input data in low frequency and those of input data in high frequency are very different. For example, when oversampling low frequency data, jitter becomes relatively fast because of the low input frequency (phase tracking circuitry uses a clock whose frequency is the same as or has a linear relationship to that of the data). So, the phase tracker has to decide quickly (e.g., to change a sampling position) in order to track the input changes correctly. In addition, when oversampling low frequency data there is typically not much noise in the input signal and the signal is typically quite clean. Inter-symbol interference is also small in low frequency data. The inventors have recognized that when the input data have relatively low frequency, it is unnecessary to use a low-pass filter in the phase tracking decision procedure (as conventionally use to prevent wrong decisions due to noise) and a low-pass filter can cause incorrect sampling position selection (typically due to the added delay in the decision process).
On the other hand, when oversampling high frequency data, jitter becomes relatively slow since the phase tracker's clock becomes relatively fast (in synchronization with the high frequency input data) so that the phase tracker has more time in clock cycles before making a decision (e.g., to change a sampling position). However, there is much higher frequency noise due to high-speed operation and this noise may lead incorrect decisions in phase tracking. Thus, to prevent a phase tracker from moving its pointer based on a small number of (e.g., one or two) incorrect input data values caused by noise, it is conventional to use a low-pass filter. The different characteristics in different frequency ranges (of the input data) make it very difficult to implement a phase tracker with good performance at both input data frequency extremes.
For example, the system described in U.S. Pat. No. 5,905,769 performs 3× oversampling of a data signal having data period P, where P=1/(the data signal's bit rate). The phase tracker of this system operates on sample groups, each sample group including twelve samples indicative of four consecutive data periods (bits) of the data signal. Each sample group consists of a first subset of four samples having phase φ(i.e., the first, fourth, seventh, and tenth samples in the sample group), a second subset of four samples having phase (φ+120 degrees (i.e., the second, fifth, eighth, and eleventh samples in the sample group), and a third subset of four samples having phase φ+240 degrees (i.e., the third, sixth, ninth, and twelfth samples in the sample group). The phase tracker does not move its pointer (to change the sampling position to a new sampling position having increased phase) unless the samples of each of four consecutive sample groups indicate that the phase of the sampling clock (the sampling position) phase lags the center of the data eye, and does not move its pointer (to change the sampling position to a new sampling position having decreased phase) unless the samples of each of four consecutive sample groups (sampled during an interval having total duration equal to 16 data periods) indicate that the sampling clock phase leads the center of the data eye. The phase tracker thus implements a low-pass filter in the sense that it ignores phase difference between the sampling clock and data signal (and does not move its pointer) unless the sampling clock phase leads (or lags) the center of the data eye for not less than 16 consecutive data periods. The inventors have recognized that this low-pass filter can cause incorrect sampling position selection when the input data has relatively low frequency.
A second issue that complicates phase tracker design concerns dead cycles that can occur during pipelined processing. The expression “dead cycle” is used herein to denote a clock cycle, that occurs during pipelined processing of input data to select a best sampling position, in which the output of the pipeline is invalid due to lack of available feedback (where the feedback is needed to generate a valid output). For example, consider a pipelined phase tracker having four stages (stages 1, 2, 3, and 4), in which stage 1 selects information that will be used in stage 2 based on a current tracking pointer which identifies a best sampling position. In stages 2 and 3, more processing is performed on the output of stage 1. In stage 4, a new (updated) tracking pointer (which determines an updated best sampling position) is generated based on the output of stage 3, and the tracking pointer generated in stage 4 is fed back to stage 1. This kind of pipeline is conventionally used to implement a phase tracker that operates at high speed. However, due to the design and feedback path of this kind of pipeline, three dead cycles occur during operation of the pipeline. To understand this, assume that data A, B, C, D, and E are the first five quantities of data asserted sequentially to stage 1. At one point in time, a tracking pointer determined by data A has just been generated in stage 4, data determined by data B are in stage 3, data determined by data C are in stage 2, and data D are in stage 1. However, the data in stages 1, 2, and 3 are invalid at this time, because a tracking pointer (generated in stage 4 in response to input data) was not available in stage 1 when data A, B, C, and D were asserted to stage 1. No valid tracking pointer is available in stage 1 until the initial tracking pointer (generated in response to data A) is asserted to stage 1 for use in processing data E. Thus, the first three clock cycles (in which data B, C, and D were asserted to stage 1) after the initial clock cycle (in which data A were asserted to stage 1) are “dead cycles.”
It is desirable to reduce the number of dead cycles that occur during operation of a pipelined phase tracker. Ideally, there will be zero dead cycles. However, due to the feedback loop (from the pointer adjustment step, or stage, to the data selection step, or stage) typically implemented in a phase tracker and the required high-speed clock frequency, it is not easy to remove stages of the pipeline to reduce the number of dead cycles to a value approaching zero (e.g., removal of pipeline stages of phase tracking circuitry to reduce the number of dead cycles results in an increased clock cycle time, which is typically unacceptable). Though it is possible to implement part or all of a phase tracker in a feed-forward manner rather than a feedback manner, this increases the hardware complexity significantly and also increases power consumption. Thus, there is a need for a phase tracker (of a feedback type) implemented to have a reduced number of dead cycles without increasing the clock cycle time.
A third issue that complicates phase tracker design arises when, as is typical, the phase tracker must operate in response to input data having a variable average number of transitions (per unit time). For example, during oversampling of TMDS-encoded data, the data are sometimes indicative of transition-minimized code words (i.e., when DE=1) and sometimes indicative of transition-maximized code words (i.e., when DE=0). A sequence of transition-maximized code words has a greater average number of transitions (per unit time) than a sequence of transition-minimized code words having the same bit rate. During oversampling of TMDS-encoded data, the phase tracker must correctly handle both transition-minimized code words (when DE=1) and transition-maximized code words (when DE=0). However, a problem arises because phase tracking uses and actually needs transitions to track the input correctly. If a phase tracker is designed to have maximized performance for transition-maximized input data (e.g., if the phase tracker changes its pointer to cause a change in sampling position only after examining samples from several consecutive input data periods), it may not perform well in response to transition minimized input data. On the other hand, if phase tracker performance is maximized for transition-minimized input data (e.g., if the phase tracker changes its pointer to cause a change in sampling position after examining samples from only one input data period or two consecutive input data periods), it may be too susceptible to possible noise in the input data. There is a need for a phase tracker that is implemented to handle input data of at least two different types, each type having a significantly different average number of transitions (per unit time). It is also possible that the optimum sample locations are different when the data has transition maximized edges than when the data has transition minimized edges due to the group velocity difference among different spectral components in the data. In that case, detecting the temporal density of transitions and having different default sample locations depending on the temporal density of transitions can provide better tracking.
Preferred embodiments of the present invention address all three above-noted issues.